This disclosure is related to memory devices within computing platforms.
Computing platforms typically include one or more dynamic random access memory (DRAM) devices. DRAM devices may be used in a variety of contexts, including main system memory and/or graphics memory, to list a couple of examples. For some computing platforms, one or more DRAM devices may be coupled to a graphics processing unit (GPU). The GPU may be located on a motherboard for some platforms, and for other platforms the GPU may be located on an adapter card.
For some computing platforms, a GPU may be coupled to one or more x16 or x32 DRAM devices. The term “x16” denotes a memory device having a 16 bit data interface and the term “x32” denotes a memory device having a 32 bit data interface. Typically, the DRAM devices have a multiplexed address bus in which a row address is sent from a memory controller located in the GPU to the DRAM and then one or more cycles later a column address is sent to the DRAM. At least in part in response to the row and column addresses, the DRAM device may retrieve data from an array of storage locations and place the data on a data bus for delivery to the GPU. For some computing platforms, the GPU may have a 64 bit data bus. For the cases where x16 DRAM devices are used for graphics memory, 4 DRAM devices may be coupled to the GPU. For cases where x32 DRAM devices are used, 2 DRAM devices may be coupled to the GPU.
DRAM devices may output data in a burst fashion. Some DRAM devices may burst groups of 4 or 8 data bits for each data output line per column address. In order to increase overall memory subsystem performance, burst lengths may increase. As burst lengths increase, the column access granularity increases which may result in a memory controller taking more data than it needs from the DRAM. For some GPUs, a sub-partition scheme may be implemented to help improve efficiency. Such a sub-partition scheme may send unique address bits to each DRAM for a subset of the total address width. For example, the total number of address inputs for a DRAM may be 13. For the case where two x32 DRAM devices are used, in order to provide a unique address to each DRAM device, 26 address lines would be required. If a 4 bit sub-partition scheme is implemented, the total number of address signals output by the memory controller increases from 13 to 17.
FIG. 1 depicts an example sub-partition scheme. A memory subsystem 100, perhaps a graphics memory subsystem, includes a memory controller 110. Memory controller 110 for this example is coupled to memory devices 120 and 130. For this example, memory devices 120 and 130 comprise x32 DRAM devices. A data bus 111 is coupled between memory controller 110 and memory devices 120 and 130. For this example, data bus 111 comprises data lines capable of delivering 64 bit s of data at a time. For this example, an address bus 121 provides 9 address lines to both memory device 120 and memory device 130. A 4 bit sub-partition address bus 123 is coupled to memory device 130, and a separate 4 bit sub-partition address bus 125 is coupled to memory device 120. For this example, memory controller 110 may deliver a row address to memory devices 120 and 130 using address bus 121 and sub-partition address busses 123 and 125. For this example, sub-partition address busses 123 and 125 have identical row address information. Also for this example, memory controller 110 may deliver column address information to memory devices 120 and 130. For this example, sub-partition address busses 123 and 125 have different column address information, allowing memory controller 110 to individually address different columns in memory devices 120 and 130. The ability to deliver sub-partitioned column addresses to the memory devices may result in improvements in efficiency. However, as x64 or greater DRAM devices become more common, the prior sub-partition schemes become inoperable because the full 64 bits of data for this example may be delivered by a single DRAM device. The prior sub-partitioning schemes require multiple DRAM devices per interface.